1. Field of the Invention
The present invention relates to processor and computing architectures having a plurality of cores and, more particularly, to offloading particular functions to different ones of the cores.
2. Description of the Related Art
Modern processors have evolved to multi-core architectures which utilize two or more on-chip processing cores (cores) per physical chip or manufacturing unit. Typically, multi-core processors are well suited to perform parallel programming operations such as matrix operations. Examples of such operations can include graphics, image processing, or cryptographic functions. The suitability of multi-core architectures in handling general business applications, however, is somewhat of an open issue. Such is the case as the identification of a particular multi-core architecture that is better, or perhaps best, suited to handle general business applications has not yet been determined. Further, the suitability of a given architecture may vary based upon the particular functions to be performed.
One proposed multi-core architecture places a plurality of homogeneous cores on a processor. Each core is configured to perform general functions. In other words, the cores are not optimized for a particular purpose. This architecture allows the same software to execute on each core, thereby facilitating concurrent execution of the same application code. Homogeneous core architectures have become popular, in part, due to the fact that software modifications are not required as each core utilizes the same instruction set.
One disadvantage of this approach is that performance optimization is difficult as each core is treated in the same manner. For example, temporal and spatial locality cannot be easily exploited at the core level since the entire application stack (e.g. system drivers, operating system processes, operating system services, business logic, etc.) executes on the same core. Spatial locality refers to the situation in which code executed by the core is stored in a memory that is local to the core, i.e. not in general memory, but rather in a level 1 or 2 cache, for instance. Temporal locality refers to the situation in which a core switches between several diverse tasks requiring the processor to continually flush and reload its local memory, resulting in lost time.
Another proposed architecture is one in which the main, or primary, processor(s) are supplemented with one or more co-processors. Each co-processor can be optimized, or hard-wired, to perform particular functions more efficiently. Examples of co-processors can include math, graphics, and network co-processors. Co-processors of this variety are essentially hardware implementations of algorithms. In any case, the functions to which the co-processor is suited can be offloaded from the main processor to the co-processor. Offloading a function, whether a graphics, networking, or other function, is software transparent in that the main processor passes execution off to the co-processor at a level that is below that of the software.
One disadvantage of this approach, however, is that additional capacity cannot be added without adding more physical resources to the system in the form of additional co-processors. Additionally, as the workload of the system shifts from one type of function to another, for example from encrypted traffic to compressed traffic, a hard-wired co-processor cannot adapt.
It would be beneficial to provide an architecture suited for multi-core processing environments which addresses the limitations described above.